1. Field of the Invention
The present invention generally relates to computer-aided circuit design systems, and more particularly to a system and method for evaluating a netlist of an integrated circuit to identify pass FETs and determine if an excessive number are connected in series.
2. Discussion of the Related Art
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor xe2x80x9cchipxe2x80x9d in which the components are interconnected to perform a given function such as a microprocessor, programmable logic device (PLD), electrically erasable programmable memory (EEPROM), random access memory (RAM), operational amplifier, or voltage regulator. A circuit designer typically designs the integrated circuit by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and ensure performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated, electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today""s sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A xe2x80x9cnetlistxe2x80x9d is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a xe2x80x9cnetlistxe2x80x9d is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often a netlist will contain a number of circuit xe2x80x9cmodulesxe2x80x9d which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by xe2x80x9cblack boxes.xe2x80x9d As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These xe2x80x9cblack boxxe2x80x9d representations, hereinafter called xe2x80x9cmodulesxe2x80x9d, will mask the complexities therein, typically showing only input/output ports.
An integrated circuit design can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions or a mix of both. At the logical level, the behavioral description is specified using Boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are full-adders, NAND gates, latches, and D-Flip Flops.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc. (purchased by Synopsys). PathMill is a transistor-based analysis tool used to find critical paths and verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the PathMill product and other similar products. For example, there is often a need to identify certain logic gates or particular combinations of logic gates. More specifically, there is sometimes a need or desire to identify combinations of gates that are configured in such a manner that may lead to operational uncertainty or performance problems. By way of particular example, it is sometimes desirable to identify multiple, series-connected pass FETs. As is known by persons skilled in the art, the presence of multiple, series connected pass FETs in a circuit design often degrades performance of an integrated circuit by slowing the output response, or otherwise due to parasitic capacitances that are associated with the components.
Accordingly, there is a heretofore unaddressed need to provide a design tool that evaluates a netlist or other electronic file representative of an electronic circuit to identify circuit configurations that form series connected pass FETs.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a system and method for identifying multiple, series-connected pass FETs in an integrated circuit by evaluating a netlist of the integrated circuit. In accordance with one aspect of the invention, a method is implemented to evaluate a current node in the netlist to determine whether the current node is a pass gate output. If the current node is that of a static gate input, the method then identifies at least one pass FET that is channel-connected to the current node, and determines that an output node of the at least one pass FET is the same node as the current node. Thereafter, the method reassigns the current node as an input node of the at least one pass FET, and repeats the foregoing steps (beginning with identifying at least one pass FET that is channel-connected to the current node).
In accordance with a similar aspect of the invention, a method is implemented by evaluating a current node in the netlist to determine whether the current node is a pass gate input. If the node is that of a pass gate input, the method then identifies at least one pass FET that is channel-connected to the current node, and determines that an output node of the at least one pass FET is the same node as the current node. Thereafter, the method reassigns the current node as an output node of the at least one pass FET, and repeats the foregoing steps (beginning with identifying at least one pass FET that is channel-connected to the current node).
In accordance with the preferred embodiment, the methods summarized above are implemented in a software routines that are called recursively. In addition, the the step of identifying at least one pass FET preferably includes the step of evaluating a data structure for each element connected to the current node. In this regard, the step of evaluating the data structure includes examining flags within the data structure. Preferably, the flags include flags for identifying the pass FET as a single pass FET, a complementary pass FET, or a RAM pass FET. Similarly, the step of determining that an output node of the at least one pass FET further includes the step of evaluating a direction flag within a data structure of the at least one pass FET. Preferably, the direction flag may be set as either xe2x80x9cunsetxe2x80x9d, xe2x80x9cbidirectionalxe2x80x9d, xe2x80x9csource-to-drainxe2x80x9d, or xe2x80x9cdrain-to-sourcexe2x80x9d.
In accordance with yet another aspect of the present invention, a system is provided for identifying multiple, series-connected pass FETs in an integrated circuit by evaluating a netlist. The system includes means for identifying a current node that is at an endpoint of a series of pass FET devices, means for identifying at least one pass FET that is series connected to the current node, means for evaluating direction of the at least one pass FET device, and means for resetting a new xe2x80x9ccurrent nodexe2x80x9d to a channel node of the at least one pass FET that is opposite the previous xe2x80x9ccurrent nodexe2x80x9d. Preferably, the system is realized in part through a software package and each of the foregoing means is implemented through one or more software routines.